To satisfy the increasing demand for function specific devices, semiconductor manufacturers have diversified their products to accommodate different operating modes. As the storage capacity of DRAM devices increase to the 1M and 4M bit range, operating modes in addition to a basic operating mode have been developed. In 1M or 4M DRAM, the operating modes are separated into 1 bit, 4 bit, 8 bit, etc., according to the desired output data and are separated into a fast page mode, a nibble mode, a static column mode, etc., according to an input control signal. Therefore, to satisfy the user's demands, the DRAM suppliers are providing a diversified line of DRAMs which perform the different operating modes according to various selected modes by optionally providing the specific operating modes in addition to the basic operating mode of DRAM during the manufacturing process. For example, in a single DRAM manufacturing line, the fast page mode may be the basic operating mode and the nibble mode or the static column mode may be optionally produced during the manufacturing process.
An optional provision is performed wafer by wafer during the production of DRAMS. After the DRAM is manufactured, the wafer is separated into individual dies or chips through a scribing process. Next, these chips are sorted according to their specific operational modes. The chips are then packaged into a tailored package through the processes of die mounting, wire bonding and molding. The packaged DRAM is marked with the product data (i.e., the serial number, manufacture date and manufacturing line) and forwarded as a final product.
Unfortunately, since the DRAMs are manufactured in a single manufacturing line, the chips having one type of operational mode are often mixed up during the chip sorting process with chips having other types of operational modes. As a result, the chips having the nonconforming operating modes are deemed erroneous during the testing step and treated as an article of inferior quality. Thus, the production yield is reduced.
To prevent the chips having the different operating modes from being mixed, very careful attention is required during the sorting process, thereby reducing manufacturing operation efficiency. Accordingly, a technique is needed which identifies the various chips during the testing step.
Techniques for identifying semiconductor chips have been disclosed in U.S. Pat. Nos. 4,150,331 and 4,510,673. U.S. Pat. No. 4,150,331 describes a technique which identifies each chip by using a programmable circuit device on the chip surface. The circuit device programs an identification code according to whether or not a diode is formed between an additionally provided test and diagnostic pin and a selected input/output pin.
However, this technique is disadvantageous in that an extra test pin is required. Thus, the package size is larger which increases the unit price of the chip.
U.S. Pat. No. 4,510,673 discloses a technique which employs a laser apparatus to place a specific identification mark (e.g., the serial number, manufacturing line, and date) on the back surface of the semiconductor chip. The identification mark may then be identified by a laser or optical apparatus. However, this technique is disadvantageous in that an expensive laser apparatus is required to mark the chips.